Spatially Placed Arbiter PUFs on an FPGA for UAV Swarm Sensing Nodes: A Proof-of-Concept Evaluation

Source abstract

Spatially placed Arbiter Physical Unclonable Functions (APUFs) exploit FPGA placement diversity to generate placement-dependent challenge–response mappings while preserving an identical logical architecture. This work presents a proof-of-concept evaluation of twenty fine-grained spatial profiles of an eight-chain, eight-stage APUF. Each profile was implemented and measured separately using one full-device configuration, and all 256 challenges were evaluated with twenty repeated measurements per profile. On the first Xilinx VC709 board, the prototype achieved 99.8843% mean raw-bit reliability, 99.0820% mean 8-bit block reliability, 47.9858% majority-response uniformity, and 47.6514% mean inter-placement uniqueness. The same twenty constrained implementations were evaluated on a second VC709 board solely to investigate cross-device behavior. Corresponding profiles on the two boards differed by 2.0703% on average, whereas the 380 nonmatching cross-device profile pairs differed by 47.6537% on average. The largest corresponding-profile distance was 3.5645%, while the smallest nonmatching-profile distance was 35.4492%, yielding an empirical separation of 31.8847 percentage points. These results indicate that deterministic placement and routing define the dominant profile personality, while device-specific manufacturing variation contributes a smaller residual. The present work does not implement concurrent multi-APUF operation or an end-to-end authentication protocol. The measurements instead motivate near-term work in which twenty or more qualified APUFs are instantiated concurrently on one FPGA, selected instances provide wider stable internal response material, and a cryptographic key-derivation process supplies 128-bit keys for an Ascon-AEAD128-protected UAV authentication and sensor-data channel.