FOLD: A Framework for On-Device Line-Segment Detection on STM32 Microcontrollers

Source abstract

The feasibility of executing learned line-segment detectors on microcontroller-class hardware has remained an open question, despite their proven accuracy on graphics processors and the emergence of compact variants such as MiLSD that is ostensibly sized for embedded memory budgets. This work proposes FOLD (Framework for On-Device Line-Segment Detection), an end-to-end deployment methodology for fully-convolutional line detectors. The framework bridges the gap between network representation and on-chip execution across the STM32 family. It is validated on actual hardware at four operating points: a 25k-parameter F-Clip baseline on an STM32F746, MiLSD across four STM32H7 boards, and two NPU-native detectors (NPLSD-M and NPLSD-H) on an STM32N6.On the STM32H7B3, int8 MiLSD runs at 10.6 s per inference with an 847 KB on-chip arena. The same model cannot be deployed on the faster STM32H743 due to fragmented SRAM, confirming that memory layout, not capacity, governs deployability. On the NPU class, a key finding is that int8 quantization, not a convolutional graph alone, engages the accelerator. In int8, NPLSD-H runs in 33.7 ms at sAP10=35.9 entirely in on-chip SRAM, a 698× speedup over MiLSD. NPLSD-M reaches sAP10=41.1 in 121.7 ms. The framework yields a measured tier map from CPU-only boards to a real-time NPU operating point. An edge-GPU reference (LINEA-N on Jetson Xavier NX: sAP10=63.9 at 101 ms, 1.34 J) bounds the map from above. All on-chip outputs match the reference models to cosine 1.000.